Arteris

About the Company

Arteris (Nasdaq: AIP) a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Vertical applications include automotive, communications, consumer electronics, enterprise computing, and industrial applications, leveraging horizontal technologies such as AI/ML, functional safety and reliability, and hardware/software integration. Arteris network-on-chip (NoC) interconnect IP and IP deployment technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.

Arteris is broadly used by market-leading customers, with over 600 systems-on-chip design starts, resulting in over 3 Billion chips shipped.

Listed Jobs

Company Name

Arteris

Job Title

Intern HDL Design Engineer automatically generated by an EDA tool / Stage Ingénieur Design HDL généré automatiquement par un outil EDA H/F

Job Description

**Job Title:** Intern HDL Design Engineer **Role Summary:** Provide HDL development and functional verification support for a serialisation library of hardware functions. Design and implement SystemVerilog/Verilog modules, automate parameterisation with Python, and create C++‑based testbenches. **Expectations:** - 6‑month internship commencing February 2026. - Bachelor’s+5 level (Master’s) engineering student in microelectronics or related field. - Opportunity for full‑time employment upon successful completion. **Key Responsibilities:** - Analyze hardware functions to be serialised and determine serialisation architecture considering physical constraints. - Translate designs into HDL code (SystemVerilog/Verilog) with an object‑oriented, functional style. - Automate parameter generation using Python scripts. - Develop and maintain C++ testbenches for functional verification. - Validate architectures through comprehensive functional verification. - Collaborate within a multicultural R&D team and adhere to industry best practices. **Required Skills:** - Proficiency in HDL (Verilog or SystemVerilog). - Experience with object‑oriented programming in Python. - Ability to write C++ code for verification and testbench development. - Familiarity with version control systems (Git). - Strong analytical and problem‑solving skills. - Good written and spoken English. **Required Education & Certifications:** - Current enrollment in a Master’s‑level engineering program (Bac+5) with a focus on microelectronics, digital IC design, or equivalent. - No specific certifications required.

Montigny-le-bretonneux, France

On site

Fresher

10-12-2025

Company Name

Arteris

Job Title

Intern Verification /Stage Vérification H/F

Job Description

Job title: Verification Internship (Stage Verification H/F) Role Summary: Intern responsible for designing and implementing a highly configurable memory test bench directly integrated into an AI‑driven Network‑on‑Chip (NoC) verification tool, ensuring delivery quality of IC designs through advanced UVM, Python, C++ modeling and verification techniques. Expactations: • Completion of a 6‑month internship program with the possibility of full‑time employment upon successful evaluation. • Demonstrate proficiency in modern object‑oriented and functional programming, digital circuit design, and verification methodology. • Deliver measurable improvements to existing NoC routing algorithms, reducing cross‑domain traversals, increasing execution speed, and enhancing test coverage. Key Responsibilities: - Take ownership of current routing algorithm and integrate it into the test bench pipeline. - Modify and extend routing logic to detect and avoid incompatible clock/power domains. - Optimize algorithm to minimize the number of domain crossings and improve runtime performance. - Develop and execute UVM‑based test cases for memory and NoC subsystems. - Collaborate with design and verification teams to validate design intent against industry standards. - Document changes, performance metrics, and propose new verification strategies. Required Skills: - Strong programming in C++ (mandatory), Python, and familiarity with JavaScript or other modern languages. - Solid understanding of object‑oriented and functional programming paradigms. - Experience in digital IC design, NoC architecture, and verification methodology (UVM). - Knowledge of combinatorial optimization and operation research concepts is an advantage. - Proficient in Linux‑based development environments. - Good written and spoken English; French language skills beneficial. Required Education & Certifications: - Current enrolment in the final year of an engineering or university program (Bac + 5) specializing in Computer Science and/or Microelectronics. - Academic record demonstrating proficiency in programming, digital design, and verification. - No formal certifications required, but experience with verification tools and digital design workflows is desirable.

Montigny-le-bretonneux, France

On site

Fresher

10-12-2025

Company Name

Arteris

Job Title

Intern Software Engineer / Stage Ingénieur software LLM H/F

Job Description

**Job Title** Intern Software Engineer – AI‑Enabled NoC Knowledge Base (Stage Ingénieur Software LLM H/F) **Role Summary** Develop and implement a specialized knowledge base to be consumed by a large‑language‑model (LLM) agent for automatic Network‑on‑Chip (NoC) architecture generation. Work at the intersection of software engineering and integrated‑circuit design, delivering state‑of‑the‑art data infrastructure and algorithmic solutions that enable real‑time knowledge retrieval, synthesis, and auto‑update from heterogeneous sources. **Expectations** By the end of the 6‑month internship, the candidate will demonstrate: - Proficiency in functional and object‑oriented programming with modern languages (C++, Python, JavaScript). - Ability to architect and develop complex software systems. - Experience designing digital circuitry and NoC interconnect topologies. - Competence in creating algorithms for complex problem resolution. - Understanding of LLM architectures and practical machine‑learning integration. - Effective use of Linux development tools and collaborative workflows. **Key Responsibilities** 1. Design, build, and deploy a performant knowledge‑base schema tailored for LLM consumption. 2. Implement data ingestion pipelines that aggregate, index, and normalize information from diverse sources. 3. Develop automated update mechanisms to refresh the knowledge base as new data arrives. 4. Propose and experiment with innovative indexing, retrieval, and synthesis techniques that improve LLM query efficiency. 5. Collaborate with the NoC algorithm team to integrate the knowledge base into the automatic NoC generation workflow. 6. Document architecture, code, and operational procedures; present findings to senior team members. **Required Skills** - Object‑oriented and functional programming (C++, Python, JavaScript). - Machine‑learning fundamentals, especially modern LLM architectures (e.g., transformer‑based models). - Integrated‑circuit design experience, including NoC topology and verification (UVM, system‑on‑chip interconnect architecture). - Proficient in Linux operating systems and associated development tools. - Strong analytical and problem‑solving abilities. - Excellent written and spoken English; teamwork and communication skills. **Required Education & Certifications** - Final year or graduate student (Bachelor +5) in Computer Science, Electrical/Electronics Engineering, Microelectronics, or a related field. - Coursework or projects involving software development, digital circuit design, and machine‑learning. - No specific certifications required.

Montigny-le-bretonneux, France

On site

Fresher

01-01-2026

Company Name

Arteris

Job Title

Intern Software Engineer / Stage Ingénieur software H/F Routage de connexions

Job Description

**Job Title** Intern Software Engineer / Stage Ingénieur software H/F Routage de connexions **Role Summary** Internship focused on enhancing and developing routing algorithms for Network‑on‑Chip (NoC) systems, ensuring minimal traversal of clock and power domains. The role blends software development with digital IC design, requiring knowledge of C++ programming, system architecture, and combinatorial optimization. **Expectations** - Deliver functional, object‑oriented code that improves existing routing solutions. - Reduce the number of distinct domains traversed in NoC paths. - Optimize algorithm execution speed. - Gain experience in both software engineering and IC design. **Key Responsibilities** 1. Analyze and understand current NoC routing algorithms. 2. Modify the routing algorithm to detect and avoid incompatible clock and power domains. 3. Enhance routing logic to minimize domain crossings. 4. Profile and optimize algorithm performance for faster execution. 5. Collaborate with design engineers to integrate software solutions into the IC design flow. **Required Skills** - Proficiency in C++ (mandatory); familiarity with Python or JavaScript is a plus. - Strong grasp of object‑oriented and functional programming concepts. - Basic knowledge of digital IC design and CPU architecture. - Understanding of combinatorial optimization or operations research methodologies. - Linux operating system proficiency. - Effective communication in English. **Required Education & Certifications** - Current enrollment in the final year of an engineering or university program (Bac+5) with a focus on Computer Science, Electronics, or Microelectronics. - Academic record demonstrating competency in programming and digital circuit design.

Montigny-le-bretonneux, France

On site

Fresher

09-01-2026